Include TOC for Verilog seriesHEADmaster

1 files changed, 2 insertions, 0 deletions

diff --git a/_posts/2026-01-06-getting-started-with-verilog.md b/_posts/2026-01-06-getting-started-with-verilog.md
index 994699b..e3b3e14 100644
--- a/_posts/2026-01-06-getting-started-with-verilog.md
+++ b/_posts/2026-01-06-getting-started-with-verilog.md
@@ -7,6 +7,8 @@ lang: en
 description: "First experiments with Verilog, mostly simuluated."
 ---
 
+{% include verilog.md %}
+
 After I got my [FPGA dev board]({% post_url 2025-12-26-fpga-dev-board %}), I
 have several books in my virtual library (Humble Bundle etc.) and decided to
 start with Verilog. The book contained a few exercises which I tried to