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| author | uvok cheetah | 2026-06-14 18:40:15 +0200 |
|---|---|---|
| committer | uvok cheetah | 2026-06-14 18:40:15 +0200 |
| commit | a40fbb874e226bf5368c8e5435fc322aa5d41a70 (patch) | |
| tree | 9c23cbc8eba6c81a9617d19ce6d71ff67712d16e /_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md | |
| parent | b3fae5622be937bf35a13325737beee1e3aaf923 (diff) | |
Rename verilog series include
Diffstat (limited to '_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md')
| -rw-r--r-- | _posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md b/_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md index 63d8951..539271e 100644 --- a/_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md +++ b/_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md @@ -7,7 +7,7 @@ date: 2026-03-22 16:55 +0100 description: How to write a CPU in Verilog --- -{% include verilog.md %} +{% include series_verilog.md %} A.k.a. "What's a fetch-decode-execute" cycle? |